1. Field of the Invention
The present invention relates, in general, to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a densely-packed contact-hole pattern in a semiconductor device.
2. Description of the Related Art
In response to the miniaturization of semiconductor devices, it becomes more difficult to form microscopic patterns by lithography techniques. For this, there are self-align double pattern techniques, in which the line pitch can be halved by forming spacers on a sidewall, which has a pattern achievable by a lithography technique, followed by processing using the spacer as a mask (JP 2008-27978 A, and JP 2008-91925 A). In addition, there is a self-align double patterning technique devised by applying the above techniques to a dense contact-hole pattern. In the fourth example of JP 2008-91925 A, there is disclosed a method forming a column of rectangular contact-holes, which has a half pitch of a column of initial rectangular patterns (first hard mask patterns).
However, in such techniques, the size of the gap formed between the spacers varies depending on the size of the initial pattern. Therefore, there is a problem in that it is difficult to set the gap size to be uniform. In addition, in the case of intending to form more densely-packed holes, that is, to form a capacitor in a dense pattern, such as 6F2 type, in a semiconductor memory device such as Dynamic Random Access Memory (DRAM), the shapes of the resultant holes are classified into two types, including a shape to which the initial pattern shape is reflected and a shape to which the spacer gap shape is reflected.